EXAM #2 FOR LOGIC DESIGN                               Fall 1996


NAME: ______________________________________

SSN: _______________________________________

CODE NAME: _________________________________ (optional)

Welcome to exam #2 for Logic Design.  You have exactly 75 minutes
to complete the seven required problems (each worth 14 points)
and the one extra credit problem (worth 7 points).  You may have
with you one 8.5 x 11 inch sheet of paper with anything on it.
Be sure to show your work.  Good luck!!!


PROBLEM #1:

Implement the following functions using a single 3-to-8 decoder.
You may use AND and OR gates, however your implementation should
be minimized.

  f1(a,b,c) = ab + abc + a'b'c'
  f2(a,b,c) = a + bc


PROBLEM #2:

Find the minterm list of the function realized by the following
circuit (assume that x1 is MSb, x2 is LSb for the shown 4-to-1
multiplexor).

         +-----+             4-to-1 Mux
   B ----+  OR |            +-----------+
         |     +------------+0          |
   C ----+     |            |           |
         +-----+   0  ------+1          |
                            |           +------- f
         +-----+   A' ------+2          |
   A  ---+ XOR |            |           |
         |     +------------+3  x1  x2  |
   B' ---+     |            +---+---+---+
         +-----+                |   |
                                A   B


PROBLEM #3:

Design a 4-to-2 priority encoder using AND and OR gates.  Your
circuit should have 4 inputs and 2 outputs.  You need not
implement the "GS" and "EO" outputs.  Assume that both positive
and negative inputs are available.


PROBLEM #4:

Design a BCD adder which adds two BCD digits and produces a BCD
results and a carry output.  Assume that you are given 4-bit
adders (with carry-in and carry-out), AND gates, OR gates, and
NOT.  Hint: Think about what needs to happen when the sum of two
four-bit values is greater than 9.


PROBLEM #5:

Implement a 1-bit half-adder using a PLA.  The PLA you are given
has three inputs, an AND array containing 4 gates, and an OR arry
containing 3 gates.


PROBLEM #6:

Given a D flip flop and NAND gates, construct a T flip flop.


PROBLEM #7:

Complete the following timing diagram for a trailing-edge
triggered JK flip flop.


       |
      1|  +--+  +--+  +--+  +--+  +--+  +--+  +--+  +--+  +--
 Clk  0|--+  +--+  +--+  +--+  +--+  +--+  +--+  +--+  +--+
       |
      1|
 J    0|
       |  >>> See solutions for this hand-drawn diagram <<<
      1|
 K    0|
       |
      1|
 Q    0|--
       |
       +------------------------------------------------------


EXTRA-CREDIT:

Design a logic circuit that multiplies two 2-bit binary numbers.
You are given half-adders, full-adders, AND, OR, and NOT.