Outline for Computer Logic Design
This is the tentative schedule for Computer Logic Design for Fall
2001.
- M 08/27 - Introduction to Logic and Computer Design / Number Systems
- W 08/29 - Number Systems and Codes (Ch. 1)
- M 09/03 - Labor Day holiday
- W 09/05 - Boolean Algebra (Ch. 2)
- M 09/10 - Switching Functions and Circuits
- W 09/12 - Logic Gates
- M 09/17 - Combinational Logic Design (HW #3 due)
- W 09/19 - Minimization Techniques using Karnaugh Maps (Ch. 3)
- M 09/24 - Minimization Techniques using Tabular Methods
- W 09/26 - Combinational Logic Circuits (Ch. 4)
- M 10/01 - Arithmetic Circuits
- W 10/03 - Logic circuit design using multiplexers, etc (Ch. 4)
- M 10/08 - Programmable Logic Devices (Ch. 5 - HW #4 due)
- W 10/10 - Exam review including examples
- M 10/15 - Exam #1 (Ch. 1 thru 5)
- W 10/17 - Exam #1 solutions, Sequential Devices (Ch. 6)
- M 10/22 - Latches and Flip Flops
- W 10/24 - Latches and Flip Flops / Timing Diagrams (HW #5 due - pop quiz)
- M 10/29 - Modular Sequential Logic (Ch. 7)
- W 10/31 - Modular Sequential Logic / Shift Registers (pop quiz)
- M 11/05 - Counters / Analysis of Sequential Logic (Ch. 8 - HW #6 due)
- W 11/07 - Analysis of Sequential Logic (pop quiz)
- M 11/12 - Veteran's Day holiday
- W 11/14 - Synthesis of Sequential Logic (HW #7 due)
- M 11/19 - Sequential Circuit Design (pop quiz)
- W 11/21 - Exam review including examples (HW #8 due)
- M 11/26 - Exam #2 (Ch. 6 thru 8)
- W 11/28 - Exam solutions, Simplification of Sequential Circuits (Ch. 9 - HW #9 due)
- M 12/03 - Lab quiz in class and Introduction to Logic Testing (Ch. 12)
- W 12/05 - Course review (HW #10 due)
Note: The final exam is comprehensive (Ch. 1 thru 9 and 12).
Last updated by
Ken Christensen on OCTOBER 1, 2001