FINAL EXAM FOR DIGITAL SYSTEMS                       Summer 1996



NAME: ___________________________   CODE NAME: __________________


Welcome to the final exam for Digital Systems.  You have exactly
two hours to complete the six required problems and the one extra
credit problem.  You may have with you one 8.5 x 11 inch sheet of
paper with anything on it.  Do not get bogged-down on any one
problem, you will have to work fast to complete this exam.  Be
sure to show your work.  Good luck and ask questions if you do
not understand a problem.


PROBLEM #1 (15 points) (10 minutes)

A black box has three boolean inputs x, y, and z, and one output
f(x,y,z).  The output is a 1 only when all three inputs are 0 or
all three inputs are 1.  Assume that the input combination x = 0,
y = 1, z = 1 can never occur.  Given only 2-input AND and OR
gates, design a circuit with a minimum number of gates that
realizes the function of the black box.  Assume that both
positive and complemented inputs are available.


PROBLEM #2 (15 points) (10 minutes)

Design a full adder with an absolute minimum of components.
Assume that you have available only the following components,
4-to-1 multiplexers and 2-input NAND gates.


PROBLEM #3 (15 points) (10 minutes)

Design a Product-of-Sums (POS) circuit with a minimum number of
gates to implement the following multiple output circuit:

  f1(x,y,z) = x'y' + xz + y'z
  f2(x,y,z) = xy'z'
  f3(x,y,z) = yz'

Note that "'" is complement as in x' is complement of x.  Assume
that you have 2- and 3-input AND and OR gates.  Assume also that
both positive and complemented inputs are available.


PROBLEM #4 (15 points) (15 minutes)

A new latch has been invented called the "MN" latch.  This new
latch behaves as follows (Q is present state, Q+ is next state):

    Q   Q+ | M  N
  ---------+-------
    0   0  | 1  0
    0   1  | 0  1
    1   0  | 0  1
    1   1  | 1  0

Design a counter circuit using the MN latch that counts 00, 11,
10, and then repeats the sequence. The counter circuit has a
pulse input (i.e., the counter increments only when pulsed).


PROBLEM #5 (20 points) (30 minutes)

Design a minimized circuit using T flip flops to implement the
following error detector.  Information bits are encoded on a
single line x so as to be synchronized with a clock.  Bits are
encoded so that two or more consecutive 1's or four or more
consecutive 0's should never appear on line x.  An
error-indicating sequential circuit is to be designed to indicate
an error by generating a 1 on output line z coinciding with the
fourth of every sequence of four 0's or the second of every
sequence of two 1's.  If, for example, three consecutive 1's
appear, the output remains 1 for the last two clock periods.  Be
sure that your implementation has a minimum number of states and
that the state assignments are made intelligently.


PROBLEM #6 (20 points) (40 minutes)

A digital system consists of three subsystems A, B, and C.  A
sequence checker circuit will receive a completion pulse from
each subsystem when the subsystem has completed its task.  When
all three subsystems are done, a final check pulse is received.
On receiving the check pulse, the sequence checker circuit should
output an error pulse of "1" if the completion pulses were
received in any other order than A, B, C.  The check pulse should
also reset the circuit in preparation for another cycle of three
completion pulses.  Design the sequence checker circuit using JK
latches and AND and OR gates.  Your design need not be minimized.


EXTRA CREDIT PROBLEM (10 points) (5 minutes)

A fundamental mode circuit with one input, x, is fully described
by the following equations:

Y1 = x'y2 +x'y1                Y2 = x + y1y2

Generate the transition table.  Identify any critical races.